1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device and, more particularly, to a method of fabricating a fin field effect transistor (FinFET) using an isotropic etching technique.
2. Description of Related Art
Semiconductor devices widely employ discrete devices such as Metal Oxide Semiconductor (MOS) transistors as switching devices. As integration of the semiconductor device increases, the sizes of MOS transistors are scaled down. As a result, the channel length of the MOS transistor is reduced so that a short channel effect may easily occur.
In general, methods for highly doping channel ions within a channel region are used to prevent a threshold voltage from decreasing due to the short channel effect. However, when the channel region is highly doped, channel resistance increases to thereby reduce current driving capability. In addition, the concentration increase of the channel ions leads to an increase of an electric field between the channel region, and source and drain regions. As a result, leakage current increases between the channel region, and the source and drain regions. In particular, when a capacitor for storing charges, as in a DRAM cell, is connected to the source or drain region, the increase of the leakage current leads to deterioration of the charge retention characteristics.
Accordingly, research is widely conducted with respect to a three dimensional transistor to reduce the short channel effect. In particular, research is widely conducted with respect to a FinFET having good on-off characteristics because of its narrow channel width.
U.S. Pat. No. 6,689,650 discloses a method of fabricating the FinFET entitled “Fin Field Effect Transistor with Self-Aligned Gate”, to Gambino et al.
According to the method disclosed by Gambino et al, it has an advantage that resistance between a channel region, and source and drain regions may be reduced because a self-aligned gate may be formed in the fin. According to the method disclosed by Gambino et al, a hard mask is patterned using a typical photolithography-etching technique to form the fin. However, there exists a limitation to form the hard mask pattern having a narrow width by patterning the hard mask, using the photolithography-etching technique.
As a result, a method for forming the fin having a narrow width needs to be optimized.